Memory chiplet having multiple arrays of memory devices and methods of forming the same

ABSTRACT

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

RELATED APPLICATION

This application is a divisional application of U.S. patent applicationSer. No. 17/412,365 entitled “Memory Chiplet Having Multiple Arrays ofMemory Devices and Methods of Forming the Same,” filed on Aug. 26, 2021,the entire contents of which is hereby incorporated by reference for allpurposes.

BACKGROUND

The semiconductor industry has continually grown due to improvements inintegration density of various electronic components (e.g., transistors,diodes, resistors, capacitors, etc.). For the most part, theseimprovements in integration density have come from successive reductionsin minimum feature size, which allows more components to be integratedinto a given area.

In addition to smaller electronic components, improvements to thepackaging of components have been developed in an effort to providesmaller packages that occupy less area than previous packages. Exampleapproaches include quad flat pack (QFP), pin grid array (PGA), ball gridarray (BGA), flip chips (FC), 3-dimensional integrated circuits (3DICs),wafer level packages (WLPs), package on package (PoP), System on Chip(SoC) or System on Integrated Circuit (SoIC) devices. Some of these3-dimensional devices (e.g., 3DIC, SoC, SoIC) are prepared by placingchips over chips on a semiconductor wafer level. These 3-dimensionaldevices provide improved integration density and other advantages, suchas faster speeds and higher bandwidth, because of the decreased lengthof interconnects between the stacked chips. However, there are manychallenges related to 3-dimensional devices.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of this disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is a vertical cross-sectional view of a first exemplarystructure after formation of a first array of memory devices and priorto formation of a second array of memory devices, according to variousembodiments.

FIG. 1B is a vertical cross-sectional view of the first exemplarystructure during formation of a second array memory cells, according tovarious embodiments.

FIG. 1C is a vertical cross-sectional view of the first exemplarystructure after formation of upper-level metal interconnect structures,according to various embodiments.

FIG. 1D is a vertical cross-sectional view of a further exemplarystructure in which two arrays of memory cells have been formed over tworespective vertically adjoining interconnect-level structures, accordingto various embodiments.

FIG. 2 is a vertical cross-sectional view of an FRAM memory structure,that may be used as a component of one or more memory arrays in thestructure of FIGS. 1B-1D, according to various embodiments.

FIG. 3 is a vertical cross-sectional view of a memory structureincluding multiple arrays of memory devices on a single die, accordingto various embodiments.

FIG. 4 is a flowchart illustrating operations of a method of fabricatinga memory structure, according to various embodiments.

FIG. 5 is a flowchart illustrating operations of a method of operating amemory structure, according to various embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. Unless explicitly statedotherwise, each element having the same reference numeral is presumed tohave the same material composition and to have a thickness within a samethickness range.

The various embodiments disclosed herein are directed to a chipletarchitecture in which multiple arrays of memory cells may be formed on asingle die. Memory devices may be formed at a substrate layer in afront-end-of-line (FEOL) process, or may be formed at one or moreinterconnect levels during one or more respective middle-end-of-line(MEOL) and/or back-end-of-line (BEOL) processes. Memory devices mayinclude a grid of independently functioning memory cells formed on asubstrate. Memory devices may include volatile or non-volatile memorycells.

Volatile memory devices may include static random access memory (SRAM)cells, dynamic random access memory (DRAM) cells, etc. In contrast tovolatile memory cells, which require constant power to retain theirmemory values, nonvolatile memory cells are capable of retaininginformation when power is not applied thereto. For example, computersincluding non-volatile memory cells do not need to be booted up whenswitched on. Emerging nonvolatile memory technologies may includeresistive random-access memory (RRAM or ReRAM), magneto-resistiverandom-access memory (MRAM), ferroelectric (FE) random-access memory(FRAM, F-RAM, or FeRAM), and phase-change memory (PCM), for example.

FRAM is a random-access memory that utilizes memory cells that include aFE material to store information as FE polarization. An FE material hasan equilibrium-state bulk electric dipole moment. This occurs in solidceramics when the ground state crystal structure involves spatialseparation of ionic charges, and the unit cell lacks a center ofsymmetry. Nanoscale alignment of the microscopic electric dipole momentsis responsible for bulk ferroelectric behavior. Typically, the magnitudeof the dipole polarization and its orientation may be controlled byapplication of modest external electric fields. The change inorientation may be a good indication of the stored value.

FRAM is commonly organized in single-transistor, single-capacitor (1T1C)or two-transistor, two-capacitor (2T2C) configurations, in which eachmemory cell includes one or more access transistors. The non-volatilityof an FRAM is due to the bi-stable characteristic of the FE material inthe cell capacitor(s). The cells are typically organized in an array,such as folded-bit line, open-bit line architectures, etc., wherein theindividual cells are selected by plate line and word line signals fromaddress decoder circuitry, with the data being read from or written tothe cells along bit lines using sense amplifier circuits.

In an open-bit line architecture, for example, the bit-lines may bedivided into multiple segments, and differential sense amplifiers may beplaced in between bit-line segments. Because the sense amplifiers may beplaced between bit-line segments, to route their outputs outside thearray, an additional layer of interconnect placed above those used toconstruct the word-lines and bit-lines may be required. The foldedbit-line array architecture routes bit-lines in pairs throughout thearray. The close proximity of the paired bit-lines may provide superiorcommon-mode noise rejection characteristics over open bit-line arrays.

A folded-bit line architecture may be favored in DRAM integratedcircuits for its superior noise immunity. This type architecture isreferred to as folded because it takes its basis from the open arrayarchitecture from the perspective of the circuit schematic. The foldedarray architecture appears to remove DRAM cells in alternate pairs(because two DRAM cells share a single bit-line contact) from a column,then move the DRAM cells from an adjacent column into the voids.

Various embodiments disclosed herein may be advantageous for certaincomputing applications that require fast and very high-bandwidth memoryaccess. In applications in neuromorphic computing and machine learning,for example, multiple fast high-bandwidth memory arrays are needed. Forexample, an array of SRAM devices may be used for computing memory andan array of DRAM devices may be used for working memory. Long-termstorage may be provided, for example, by a 3-dimensional NAND array.Such a configuration, however, may have certain drawbacks. For example,latency of data transfer between the DRAM array and the 3-dimensionalNAND array may limit bandwidth performance. Similar latency may also bean be a problem with data transfer between SRAM and DRAM devices.

Various embodiments disclosed herein overcome the above-describeddrawbacks by providing a memory structure having multiple memory arraysformed on a single die. In this regard, various disclosed embodimentsmay include an SRAM memory array at a semiconductor material level of adie, a DRAM or other 1T1C array above the SRAM array, and a3-dimensional FRAM array above the DRAM or other 1T1C array. The memorystructure may further include a data bus that allows massive datainput/output (TO) between the three memory arrays (e.g., SRAM, 1T1C and3D FRAM). For example, in one embodiment the data bus may be a 1024 bitdata bus. Peripheral control devices may further be provided at thesemiconductor material layer. Such peripheral devices may be configuredto control data transfer between the various memory arrays. As the namesuggest, in some embodiments, peripheral devices may be located out onthe periphery of the memory arrays (outer edge of the memory arrayarea). However, in various embodiments, the peripheral control circuitrymay be located below the 1T1C and FRAM arrays to reduce the overall areaof the memory structure. In addition, such a configuration may allowvarious embodiments to shorten the data bus connection. In this manner,the various embodiments may improve overall device speed and bandwidthof memory access. In some embodiments, bandwidth may be increased byfactors of between 32 and 64 relative to conventional memory structures.

FIG. 1A is a vertical cross-sectional view of a first exemplarystructure after formation of a first array of memory devices and priorto formation of a second array of memory devices, according to variousembodiments. The first exemplary structure may include a substrate 8that contains a semiconductor material layer 10. The substrate 8 mayinclude a bulk semiconductor substrate such as a silicon substrate inwhich the semiconductor material layer continuously extends from a topsurface of the substrate 8 to a bottom surface of the substrate 8, or asemiconductor-on-insulator layer including the semiconductor materiallayer 10 as a top semiconductor layer overlying a buried insulator layer(such as a silicon oxide layer). The exemplary structure may includevarious devices regions, which may include a memory array region 50 inwhich at least one array of memory cells may be subsequently formed. Thememory cells may be volatile or non-volatile memory cells, as describedabove.

The first array of memory devices may include an array of SRAM cellsformed on, and/or in, the semiconductor material layer 10. One or moreadditional arrays of volatile or non-volatile memory cells may be formedat various interconnect levels above the semiconductor material layer10. Volatile memory cells may include DRAM cells and non-volatile memorycells may include RRAM, MRAM, FRAM, PCM devices, etc.

The exemplary structure may also include a peripheral logic region 52 inwhich electrical connections between each array of volatile ornon-volatile memory cells and a peripheral circuit including fieldeffect transistors may be subsequently formed. Areas of the memory arrayregion 50 and the logic region 52 may be employed to form variouselements of the peripheral circuit.

Semiconductor devices such as field effect transistors (FETs) may beformed on, and/or in, the semiconductor material layer 10 during afront-end-of-line (FEOL) operation. For example, shallow trenchisolation structures 12 may be formed in an upper portion of thesemiconductor material layer 10 by forming shallow trenches andsubsequently filling the shallow trenches with a dielectric materialsuch as silicon oxide. Other suitable dielectric materials are withinthe contemplated scope of disclosure. Various doped wells (not expresslyshown) may be formed in various regions of the upper portion of thesemiconductor material layer 10 by performing masked ion implantationprocesses.

Gate structures 20 may be formed over the top surface of the substrate 8by depositing and patterning a gate dielectric layer, a gate electrodelayer, and a gate cap dielectric layer. Each gate structure 20 mayinclude a vertical stack of a gate dielectric 22, a gate electrode 24,and a gate cap dielectric 28, which is herein referred to as a gatestack (22, 24, 28). Ion implantation processes may be performed to formextension implant regions, which may include source extension regionsand drain extension regions. Dielectric gate spacers 26 may be formedaround the gate stacks (22, 24, 28). Each assembly of a gate stack (22,24, 28) and a dielectric gate spacer 26 constitutes a gate structure 20.Additional ion implantation processes may be performed that use the gatestructures 20 as self-aligned implantation masks to form deep activeregions.

Such deep active regions may include deep source regions and deep drainregions. Upper portions of the deep active regions may overlap withportions of the extension implantation regions. Each combination of anextension implantation region and a deep active region may constitute anactive region 14, which may be a source region or a drain regiondepending on electrical biasing. A semiconductor channel 15 may beformed underneath each gate stack (22, 24, 28) between a neighboringpair of active regions 14. Metal-semiconductor alloy regions 18 may beformed on the top surface of each active region 14.

Field effect transistors may be formed on the semiconductor materiallayer 10. Each field effect transistor may include a gate structure 20,a semiconductor channel 15, a pair of active regions 14 (one of whichfunctions as a source region and another of which functions as a drainregion), and optional metal-semiconductor alloy regions 18.Complementary metal-oxide-semiconductor (CMOS) circuits 75 may beprovided on the semiconductor material layer 10, which may include aperiphery circuit for the array(s) of transistors, such as thin filmtransistors (TFTs), and memory devices to be subsequently formed.

Various interconnect-level structures may be subsequently formed, whichare formed prior to formation additional memory devices and are hereinreferred to as lower interconnect-level structures (L0, L1, L2). In someembodiments, a two-dimensional array of TFTs and memory devices may besubsequently formed over two levels of interconnect-level metal lines.The lower interconnect-level structures (L0, L1, L2) may include acontact-level structure L0, a first interconnect-level structure L1, anda second interconnect-level structure L2. The contact-level structure L0may include a planarization dielectric layer 31A including aplanarizable dielectric material such as silicon oxide and variouscontact via structures 41V contacting a respective one of the activeregions 14 or the gate electrodes 24 and formed within the planarizationdielectric layer 31A.

The first interconnect-level structure L1 may include a firstinterconnect level dielectric (ILD) layer 31B and first metal lines 41Lformed within the first ILD layer 31B. The first ILD layer 31B is alsoreferred to as a first line-level dielectric layer. The first metallines 41L may contact a respective one of the contact via structures41V. The second interconnect-level structure L2 includes a second ILDlayer 32, which may include a stack of a first via-level dielectricmaterial layer and a second line-level dielectric material layer or aline-and-via-level dielectric material layer. The second ILD layer 32may have formed there within second interconnect-level metalinterconnect structures (42V, 42L), which includes first metal viastructures 42V and second metal lines 42L. Top surfaces of the secondmetal lines 42L may be coplanar with the top surface of the second ILDlayer 32.

FIG. 1B is a vertical cross-sectional view of the first exemplarystructure during formation of a second array memory cells, according tovarious embodiments. An array 95 of volatile or non-volatile memorycells and selector devices, such as TFT selectors, may be formed in thememory array region 50 over the second interconnect-level structure L2.A third ILD layer 33 may be formed during formation of the array ofmemory cells and TFT selector devices. The set of all structures formedat the level of the array 95 of memory cells and TFT selector devicestransistors is herein referred to as a third interconnect-levelstructure L3.

FIG. 1C is a vertical cross-sectional view of the first exemplarystructure after formation of upper-level metal interconnect structuresaccording to an embodiment of the present disclosure. Referring to FIG.1C, third interconnect-level metal interconnect structures (43V, 43L)may be formed in the third ILD layer 33. The third interconnect-levelmetal interconnect structures (43V, 43L) may include second metal viastructures 43V and third metal lines 43L. Additional interconnect-levelstructures may be subsequently formed, which are herein referred to asupper interconnect-level structures (L4, L5, L6, L7). For example, theupper interconnect-level structures (L4, L5, L6, L7) may include afourth interconnect-level structure L4, a fifth interconnect-levelstructure L5, a sixth interconnect-level structure L6, and a seventhinterconnect-level structure L7.

The fourth interconnect-level structure L4 may include a fourth ILDlayer 34 having formed therein fourth interconnect-level metalinterconnect structures (44V, 44L), which may include third metal viastructures 44V and fourth metal lines 44L. The fifth interconnect-levelstructure L5 may include a fifth ILD layer 35 having formed thereinfifth interconnect-level metal interconnect structures (45V, 45L), whichmay include fourth metal via structures 45V and fifth metal lines 45L.The sixth interconnect-level structure L6 may include a sixth ILD layer36 having formed therein sixth interconnect-level metal interconnectstructures (46V, 46L), which may include fifth metal via structures 46Vand sixth metal lines 46L. The seventh interconnect-level structure L7may include a seventh ILD layer 37 having formed therein sixth metal viastructures 47V (which are seventh interconnect-level metal interconnectstructures) and metal bonding pads 47B. The metal bonding pads 47B maybe configured for solder bonding (which may employ C4 ball bonding orwire bonding), or may be configured for metal-to-metal bonding (such ascopper-to-copper bonding).

Each ILD layer may be referred to as an ILD layer 30. Each of theinterconnect-level metal interconnect structures may be referred to as ametal interconnect structure 40. Each contiguous combination of a metalvia structure and an overlying metal line located within a sameinterconnect-level structure (L2-L7) may be formed sequentially as twodistinct structures by employing two single damascene processes, or maybe simultaneously formed as a unitary structure employing a dualdamascene process. Each of the metal interconnect structure 40 mayinclude a respective metallic liner (such as a layer of TiN, TaN, or WNhaving a thickness in a range from 2 nanometers (nm) to 20 nm) and arespective metallic fill material (such as W, Cu, Co, Mo, Ru, otherelemental metals, or an alloy or a combination thereof). Other suitablematerials for use as a metallic liner and metallic fill material arewithin the contemplated scope of disclosure. Various etch stopdielectric layers and dielectric capping layers may be inserted betweenvertically neighboring pairs of ILD layers 30, or may be incorporatedinto one or more of the ILD layers 30.

While this embodiment is described in which the array 95 of memory cellsand TFT selector devices may be formed as a component of a thirdinterconnect-level structure L3, embodiments are expressly contemplatedherein in which the array 95 of memory cells and TFT selector devicesmay be formed as components of any other interconnect-level structure(e.g., L1-L7). Further, while this example is described using anembodiment in which a set of eight interconnect-level structures areformed, embodiments are expressly contemplated herein in which adifferent number of interconnect-level structures is used.

In addition, embodiments are expressly contemplated herein in which twoor more arrays 95 of memory cells and TFT selector devices may beprovided within multiple interconnect-level structures in the memoryarray region 50. While an embodiment is disclosed in which an array 95of memory cells and TFT selector devices may be formed in a singleinterconnect-level structure, embodiments are expressly contemplatedherein in which an array 95 of memory cells and TFT selector devices maybe formed over two vertically adjoining interconnect-level structures,as described in greater detail below with reference to FIG. 1D.

FIG. 1D is a vertical cross-sectional view of a further exemplarystructure in which two arrays (95 a, 95 b) of memory cells and TFTselector devices may be formed over two vertically adjoininginterconnect-level structures, according to various embodiments. In thisexample, a first array 95 a of volatile or non-volatile memory cells andselector devices (e.g., TFT selectors) may be formed in the memory arrayregion 50 over the second interconnect-level structure L2. The structureof FIG. 1D further includes a second array 95 b of volatile ornon-volatile memory cells and selector devices (e.g., TFT selectors)formed in the memory array region 50 over the fifth interconnect-levelstructure L5. As described above, one or both of the memory arrays (95a, 95 b) may include volatile memory cells (e.g., DRAM cells) or mayinclude non-volatile memory cells (e.g., FRAM cells). For example, array95 a may include DRAM or other 1T1C cells and array 95 b may includeFRAM cells. In other embodiments, arrays (95 a, 95 b) may includevarious other types of volatile and non-volatile memory cells.

FIG. 2 is a vertical cross-sectional view of a FRAM memory structure200, that may be used as a component of one or more memory arrays in thestructure of FIGS. 1B-1D, according to various embodiments. The memorystructure 200 may include a transistor 210 and a ferroelectric tunneljunction (FTJ) memory cell 220. Accordingly, the memory structure 200may have a 1 transistor—1 capacitor (1T1C) configuration. Any othersuitable configuration including more than one transistor and/or morethan one capacitor are within the scope of the present disclosure. Forexample, a memory structure may include a 2T2C configuration. Thetransistor 210 may be disposed on a substrate 202. The substrate 202 maybe a semiconductor substrate, such as an amorphous silicon orpolysilicon substrate. In other embodiments, the substrate 202 may be adielectric layer, such as an interconnect dielectric layer.

The transistor 210 may include a semiconductor layer 102 including asource region 104, a drain region 106, and a channel region 108 disposedthere between. In some embodiments the transistor 202 may be acomplementary metal oxide semiconductor (CMOS) transistor formed in aFEOL. In such embodiments, the semiconductor layer 102 may includepolysilicon, amorphous silicon, silicon, or compound including silicon.In other embodiments, the transistor 210 may also be a TFT using asemiconducting oxide, such as InGaZnO (IGZO), indium tin oxide (ITO),InWO, InZnO, InSnO, GaO_(x), InO_(x), etc. In embodiments in which thetransistor 210 is a TFT, the substrate 202 may be a layer formed duringa BEOL process.

A high-k dielectric layer 232 may be disposed on the channel region 108.In various embodiments, the high-k dielectric layer 232 may have athickness in a range from approximately 0.5 nm to approximately 5.0 nm,such as from 1 nm to 4 nm, although larger or smaller thicknesses may beused. Herein, high-k dielectric materials have a dielectric constantgreater than 3.9 and may include, but are not limited to, siliconnitride (SiN_(x)), hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO),hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafniumzirconium oxide (Hf_(0.5)Zr_(0.5)O₂) (HZO)), tantalum oxide (Ta₂O₅),aluminum oxide (Al₂O₃), lanthanum aluminate (LaAlO₃), hafniumdioxide-alumina (HfO₂—Al₂O₃), zirconium oxide (ZrO₂), magnesium oxide(MgO), combinations thereof, etc. Other suitable dielectric materialsare within the scope of the present disclosure.

A gate electrode 132 may be disposed on the high-k dielectric layer 232.The gate electrode 132 may be formed of any suitable electricallyconductive material, using any suitable deposition process.

The FTJ 220 may include a bottom electrode 120, a high-k dielectric 124,a ferroelectric layer 126, an interface metal 128, and a top electrodelayer 130.

In the memory structure 200, the source region 104 may be electricallyconnected to a bit line 240, the drain region 106 may be electricallyconnected to the bottom electrode layer 120 by a drain via contact 242,and the top electrode layer 130 may be electrically coupled to a plateline 244. The gate electrode 132 may be electrically connected to a wordline 246. A dielectric layer 230, such as an interconnect dielectriclayer, may be disposed on the substrate 202. For example, the high-kdielectric layer 232, gate electrode 132, word line 246, bit line 240,drain via contact 242, and FTJ 220 may be embedded in the dielectriclayer 230.

The ferroelectric layer 126 may include any suitable ferroelectricmaterial, such as HfO, HfO₂, ZrO₂, Hf_(0.5)Zr_(0.5)O₂ (HfZrO), HfSiO,HfLaO, AlScN, PbZrO₃ (PBT), Pb[Zr_(x)Ti_(1-x)]O₃, (0≤x≤1) (PZT),Pb_(1-x)La_(x)Zr_(1-y)Ti_(y)O₃ (PLZT), BaTiO₃, PbTiO₃, PbNb₂O₆, LiNbO₃,LiTaO₃, PbMg_(1/3)Nb_(2/3)O₃ (PMN), PbSc_(1/2)Ta_(1/2)O₃ (PST),SrBi₂Ta₂O₉ (SBT), Bi_(1/2)Na_(1/2)TiO₃, combinations thereof, etc. Insome embodiments, the ferroelectric layer 126 may be formed of HfO,HfO₂, HfZrO, PZT, PbTiO₃, HfLaO, or the like. Other suitableferroelectric materials are within the contemplated scope of disclosure.

Alternatively, the ferroelectric layer 126 may be formed by depositingan FE material using any suitable deposition method, such as PVD, spincoating and annealing, sputtering, CVD, ALD, PECVD, spray pyrolysis,pulsed laser deposition (PLD) or combinations thereof. In variousembodiments, the ferroelectric layer 126 may be a ferroelectric filmthat is thin enough to allow tunneling of electrons there through. Forexample, the thickness of the ferroelectric layer 126 may be about 1 nmto about 50 nm thick, such as from about 2 nm to about 25 nm, or about10 nm thick.

The gate electrode 132 may include an electrically conductive material,and may be formed by any suitable deposition process, with respect tothe bottom and top electrodes 120 and 130. In some embodiments, the gateelectrode 132 may include an n-type work function material, such as Ta,TiAl, etc., or may include a n-type work function material, such as TiN,WO₃, etc. The work function of the gate electrode 132 may be selectedbased on the conductivity type of the channel region 108. In otherembodiments, the gate electrode 132 may be formed using a replacementgate process. For example, the gate electrode 132 may formed to includea sacrificial material layer such as a p-doped polysilicon material,n-doped polysilicon material, a silicon-germanium alloy, amorphouscarbon or a dielectric material. In a subsequent processing step, thesacrificial material layer may be replaced with a high conductive metallayer.

In various embodiments, the source region 104 may be electricallyconnected to a source electrode or bit line through contact vias (notshown). The drain region 106 may be electrically connected to a drainelectrode through contact vias (not shown). The gate electrode 132 maybe electrically connected to a word line of a semiconductor device, suchas a memory device.

In alternate embodiments, a DRAM structure may be formed to haveessentially the same components as the FRAM memory structure 200 of FIG.2 with the exception of the ferroelectric layer 126. For example,replacement of the ferroelectric layer 126 with a dielectric or high-kdielectric results in the formation of a capacitor structure such thatthe capacitor structure coupled with the transistor 210 forms a DRAMstructure. Accordingly, a DRAM memory structure may have a 1transistor—1 capacitor (1T1C) configuration. Any other suitableconfiguration including more than one transistor and/or more than onecapacitor are within the scope of the present disclosure. For example, amemory structure may include a 2T2C configuration. A DRAM memorystructure, formed in this way, may have similar electrical connectionsto that of the FRAM memory structure 200 of FIG. 2 . In this regard, thesource region 104 may be electrically connected to a bit line 240, thedrain region 106 may be electrically connected to the bottom electrodelayer 120 by a drain via contact 242, and the top electrode layer 130may be electrically coupled to a plate line 244. The gate electrode 132may be electrically connected to a word line 246.

In still further embodiments, the high-k dielectric layer 232 in FIG. 2may be replaced with the ferroelectric material to thereby form aferroelectric field-effect transistor (FeFET). In such an embodiment,the FTJ structure 220 may be omitted and the FeFET structure may beconfigured as an FRAM memory device.

FIG. 3 is a vertical cross-sectional view of a memory structure 300including multiple arrays of memory devices on a single die, accordingto various embodiments. The memory structure 300 may include a firstmemory region 302 including a first array of field effect transistordevices 312, a second memory region 304 including a second array ofmemory devices 314, and a third memory region 306 including a thirdarray of memory devices 318_1, 318_2, . . . 318_n. The memory structure300 may further include at least one data bus laterally extending acrossthe first memory region 302, the second memory region 304, and thirdmemory region 306, and configured to provide data transfer among thefirst memory array, the second memory array, and the third memory array.In this regard, the data bus may include lateral interconnect structures308 a, 308 b, and 308 c as well as vertical interconnect structures 310a and 310 b. In certain embodiments, the data bus may be configured as a1024 bit data bus.

The first memory array 302 may include field effect transistor devices312 formed at the substrate material layer 10 in a front-end-of-line(FEOL) process, as described above with reference to FIG. 1A. Forexample, transistor devices 312 may be formed as CMOS circuits 75located on the semiconductor material layer 10. Some of the transistordevices 312 may be configured as SRAM memory devices. In this way, thefirst memory array may be an array of SRAM memory devices. Othertransistor devices 312 within the first memory region 302 may beconfigured to perform computing logic functions, and still othertransistor devices 312 may be configured as peripheral circuits. Theperipheral circuits formed in the first memory region 302 may beconfigured to control the first memory array, the second array, and thethird memory array in cooperation with the logic circuits in the firstmemory region 302.

The second memory region 304 may be formed above the first memory region302 on the same die and may be formed as an integrated structure, asdescribed above with reference to FIGS. 1B to 1D. In one embodiment, thesecond memory region 304 may include an array 95 (e.g., see FIGS. 1B and1C) of volatile or non-volatile memory cells and selector devices, suchas TFT selectors. As described above, the array 95 may be formed overthe second interconnect-level structure L2. In other embodiments, thearray 95 may be formed over other interconnect-level structures (e.g.,L3-L7).

The memory devices 314 formed in the second memory region 304 (e.g., seeFIG. 3 ) may include FRAM memory devices 200, or FeFET devices, asdescribed above with reference to FIG. 2 . As such, memory devices 314may include a storage device 316. In the example of FIG. 2 , the storagedevice 316 may be configured as a FTJ structure 220 including aferroelectric layer 126. In other embodiments, FTJ structure 220 mayinclude an anti-ferroelectric layer 126. Alternatively, as describedabove, memory devices 314 may be configured as 1T1C devices. Such 1T1Cdevices may have similar components as those of the FRAM structure 200with the exception of the ferroelectric layer 126. By substitution of adielectric layer, or high-k dielectric layer in place of theferroelectric layer 126, a capacitor structure may be formed in place ofthe FTJ structure 220. The resulting device may have a 1T1Cconfiguration and may be configured to operate as a DRAM device or other1T1C device. Other embodiments may include various other types of memorydevices 314 that may be configured as 1T1C devices, 2T2C devices, etc.

The memory devices 318_1, 318_2, . . . 318_n (where n is an integergreater than 2) formed in the third memory region 306 (e.g., see FIG. 3) may include various types of volatile or non-volatile memory devices.For example, memory devices 318 may include a plurality of memorydevices 318_1, 318_2, . . . 318_n configured in a stacked arrangement,as shown in FIG. 3 . In one embodiment, each of memory devices 318_1,318_2, . . . 318_n may be configured as a two-dimensional array of FRAMor FeFET devices. For example, each of memory devices 318_1, 318_2, . .. 318_n may be configured as a FRAM chip, with each FRAM chip configuredas a two-dimensional array of FRAM or FeFET devices. The verticalinterconnect structures 310 a and 310 b may be configured such that theplurality of FRAM chips 318_1, 318_2, . . . 318_n may be configured as a2.5-dimensional FRAM array.

In further embodiments, the plurality of memory devices 318_1, 318_2, .. . 318_n may be integrally formed in an BEOL process as a 3-dimensionalFRAM array. As such, the 3-dimensional FRAM array many include memorydevices 318_1, 318_2, . . . 318_n formed at various interconnect levelstructures, as described above with reference to FIGS. 1B to 1D. Forexample, the plurality of memory devices 318_1, 318_2, . . . 318_n maybe formed as the memory array 95 b formed over the over the fifthinterconnect-level structure L5, as described above with reference toFIG. 1D. Similarly, the second memory array may be formed as the memoryarray 95 a over the second interconnect-level structure L2, as describedabove with reference to FIG. 1D. In an embodiment, the first memoryarray may be formed as CMOS circuits 75 that provided on thesemiconductor material layer 10, as described above with reference toFIGS. 1A to 1D.

In the above-described example, the third memory array that is locatedin third memory region 306 (e.g., memory array 95 b in FIG. 1D) may beconfigured as a 2.5-dimensional or 3-dimensional memory array. In otherembodiments, one or both of the second memory array, formed in secondmemory region 304, and the third memory array, formed in third memoryregion 306, may be configured as a 2.5-dimensional or 3-dimensionalarray. Further, the 2.5-dimensional or 3-dimensional array may includeword lines (not shown) that are shared between a plurality of stackedactive device layers within the 2.5-dimensional or 3-dimensional memoryarray. In further embodiments, the word lines may be formed as lateralinterconnect structures that couple memory devices in a plurality ofactive device layers. In this regard, word lines may be formed as partof the lateral interconnect structures 308 a, 308 b, and 308 c. Infurther embodiments, word lines may be formed as part of the verticalinterconnect structures 310 a and 310 b.

In further embodiments, the data bus (e.g., see interconnect structures308 a, 308 b, 308 c, 310 a, and 310 b in FIG. 3 ) may include common bitlines (not shown) that may be switchably shared between the first memoryarray, the second memory array, and the third memory array. As such, thedata bus may be configured to switchably transfer data among the firstmemory array, the second memory array, and the third memory array. Inthis regard, the peripheral devices located in first memory region 302may include various bus selector switches that control connectionsbetween various parts of the data bus. For example, data may betransferred between one memory array and another memory array byswitching on connections between common bit lines that are sharedbetween the two arrays.

In one embodiment, the first memory array that is located in firstmemory region 302 may include an array of SRAM devices, the secondmemory array that is located in second memory region 304 (see alsomemory array 95 a of FIG. 1D) may include an array of DRAM, FRAM, FeFET,or other 1T1C devices, and the third memory array that is located inthird memory region 306 may include a 2.5-dimensional or 3-dimensionalFRAM array. Further, the peripheral devices located in first memoryregion 302 may be configured to provide control access across the firstmemory array, the second memory array, and the third memory arrayboundaries. As such, the data bus may be configured to selectivelycontrol data transfer between the first (SRAM) memory array and thesecond (1T1C) memory array, between the second (1T1C) memory array andthe third (FRAM) memory array, and between the first (SRAM) memory arrayand the third (FRAM) memory array. The peripheral devices may includesense amplifiers and decoder circuits for the one or more respectivefirst memory array, the second memory array, and the third memory array.The peripheral devices may further include data bus switching devicesthat may be configured to control data transfer between any of the firstmemory array, the second memory array, and the third memory array.

The above-described embodiments include peripheral devices that may belocated in the semiconductor material layer 10 (e.g., see FIGS. 1A to1D) of the die. Such devices may be a subset of transistor devices 312located in the first memory region 302 (e.g., see FIG. 3 ). Also, asdescribed above, the transistor devices 312 formed in the first memoryregion 302 may further include devices configured as logic devices toperform computing logic operations. In further embodiments, additionalperipheral devices (not shown) may be formed in the second memory region304 and the third memory region 306. These additional peripheral devicesmay be formed as TFT devices in a BEOL process, as described above. SuchTFT devices, formed at the second memory region 304 and at the thirdmemory region 306 may also be configured to perform logic operations.

FIG. 4 is a flowchart illustrating operations of a method 400 offabricating a memory structure, according to various embodiments. In afirst operation 402, the method 400 may include forming a first memoryarray including SRAM memory devices. As described above, the firstmemory array may be formed in the first memory region 302 as CMOStransistor devices 312 formed in the semiconductor material layer (e.g.,see FIGS. 1A to 1D). In operation 402, the method 400 may includeforming a second memory array including 1T1C devices. The second memoryarray may be formed in the second memory region 304. In otherembodiments, the second memory array may include FRAM or FeFET devices(e.g., see FIG. 2 ) or other 1T1C, 2T2C, etc., memory devices formed inthe second memory region 304. In operation 406, the method 400 mayinclude forming a third memory array including FRAM or FeFET memorydevices. The third memory array may be formed in the third memory region306 and may be configured as a 2.5-dimensional or 3-dimensional array ofFRAM or FeFET devices.

In operation 408, the method 400 may include forming at least one databus laterally extending across the first memory region 302, the secondmemory region 304, and third memory region 306. As described above, thedata bus may include lateral interconnect structures 308 a, 308 b, and308 c, as well as vertical interconnect structures 310 a, and 310 b(e.g., see FIGS. 1A to 1D, and FIG. 3 ). The data bus may be configuredprovide data transfer among the first memory array, the second memoryarray, and the third memory array.

In operation 410, the method 400 may include forming peripheral circuitdevices at a semiconductor material layer 10 of the die (e.g., see FIGS.1A to 1D). Such peripheral devices may be a subset of CMOS transistordevices 312 that may be formed in first memory region 302 (e.g., seeFIG. 3 ). The peripheral devices may include sense amplifiers anddecoder circuits for the one or more respective first memory array, thesecond memory array, and the third memory array. The peripheral devicesmay further include data bus switching devices that may be configured tocontrol data transfer between the first memory array, the second memoryarray, and the third memory array. In further embodiments, peripheraldevices may also be formed as TFT devices in the second memory region304 and the third memory region 306.

The method 400 may further include forming the data bus as a pluralityof interconnect level structures (e.g., see FIGS. 1A to 1D). Asdescribed above, the method 400 may include forming the first memoryarray as SRAM memory devices on the semiconductor material layer 10 ofthe die; forming the second memory array as 1T1C memory devices over afirst interconnect level structure of the plurality of interconnectlevel structures (e.g., over interconnect level L2 in FIGS. 1B to 1D);forming the third memory array as FRAM or FeFET memory devices over asecond interconnect level structure of the plurality of interconnectlevel structures (e.g., over interconnect level L5 in FIGS. 1B to 1D);and forming the peripheral circuit devices that may be configured toprovide control access across boundaries of the first memory array,boundaries of the second memory array and boundaries of the third memoryarray. In this regard, the method 400 may include forming the peripheraldevices to include sense amplifiers and decoder circuits for the one ormore of the respective first memory array, the second memory array, andthe third memory array. The method 400 may further include forming theperipheral circuit devices to include data bus switching devices thatare configured to control data transfer between the first memory array,the second memory array, and the third memory array.

The method 400 may further include forming TFT devices located at one orboth of the first interconnect level (i.e., in memory region 304) andthe second interconnect level (i.e., in memory region 306). The method400 may further include forming computing logic devices located on thesemiconductor material layer 10 of a die (e.g., see FIGS. 1A to 1D).Further, forming the at least one data bus may further include couplingthe computing logic devices to the first memory array, the second memoryarray, the third memory array, and the peripheral circuit devices. Themethod 400 may further include forming one or more of the second memoryarray and the third memory array as a 3-dimensional memory arrayincluding word lines that are shared between two or more stacked activedevice layers within the 3-dimensional memory array. In otherembodiments, one or more of the second memory array and the third memoryarray may be configured as a 2.5-dimensional array.

FIG. 5 is a flowchart illustrating operations of a method 500 ofoperating a memory structure, according to various embodiments. Inoperation 502, the method 500 may include receiving and storing data toa first memory array located in a first memory region 302 of a die, thefirst memory region 302 including an array of SRAM memory devices. Inoperation 504, the method 500 may further include transferring data fromthe first memory array to a second memory array located in a secondmemory region 304 of the die. In some embodiments, the second memoryregion 304 may include an array of 1T1C memory devices. In otherembodiments, the second memory region 304 may include an array of FRAMor FeFET memory devices. In operation 506, the method 500 may furtherinclude transferring data from the first memory array and/or from thesecond memory array to a third memory array located in a third memoryregion 306 of the die, the third memory region an array of FRAM or FeFETmemory devices (e.g., see FIG. 2 and related description, above).

According to method 500, the data may be transferred to and from thefirst memory array, the second memory array, and the third memory arrayvia at least one data bus laterally extending across the first memoryregion 302, the second memory region 304, and third memory region 306.Further, according to method 500, the transfer of data to and from thefirst memory array, the second memory array, and the third memory arraymay be controlled by peripheral circuit devices formed at asemiconductor material layer 10 (e.g., see FIGS. 1A to 1D) of the memorystructure.

In operation 508, the method 500 may further include controlling databus switching devices to control common bit lines that are switchablyshared between the first memory array, the second memory array, and thethird memory to thereby transmit data among the first memory array, thesecond memory array, and the third memory array via the common bitlines.

With reference to FIGS. 1A-3 , a memory structure 300 may be provided.The memory structure 300 may include: a first memory region 302 that mayinclude a first memory array of SRAM memory devices; a second memoryregion 304 that may include a second memory array of 1T1C memorydevices; a third memory region 306 that may include a third memory arrayof FRAM or FeFET memory devices; at least one data bus laterallyextending across the first memory region 302, the second memory region304, and third memory region 306 and configured to provide data transferamong the first memory array, the second memory array, and the thirdmemory array; and peripheral circuit devices formed at a semiconductormaterial layer of the memory structure 300, the peripheral circuitdevices configured to control the first memory array, the second memoryarray, and the third memory array.

In one embodiment, at least one of the second memory array and the thirdmemory array may be configured as a 3-dimensional memory array that mayinclude word lines that may be shared between a plurality of stackedactive device layers within the 3-dimensional memory array. In oneembodiment, the word lines may be formed as lateral interconnectstructures 308 a, 308 b, 308 c that couple memory devices of the3-dimensional memory array that comprises the plurality of stackedactive device layers. In one embodiment, the peripheral circuit devicesformed at a semiconductor material layer of the memory structure may belocated beneath the second memory array and beneath the third memoryarray. That is, the area used to form the peripheral circuit devicesoverlaps with the area used to form the second memory array and thethird memory array.

In another embodiment, the word lines may be formed as verticalinterconnect structures 310 a, 310 b that couple memory devices of the3-dimensional memory array that comprises the plurality of stackedactive device layers. In one embodiment, the data bus may include commonbit lines that may be switchably shared between the first memory array,the second memory array, and the third memory, the data bus configuredto switchably transfer data among the first memory array, the secondmemory array, and the third memory array. In one embodiment, the databus may include a plurality of interconnect level structures; the SRAMmemory devices of the first memory array may be located on thesemiconductor material layer 8 of the memory structure 300; the 1T1Cmemory devices may be located over a first interconnect level structureof the plurality of interconnect level structures; the FRAM or FeFETmemory devices may be located over a second interconnect level structureof the plurality of interconnect level structures; and the peripheralcircuit devices may be configured to provide control access acrossboundaries of the first memory array, boundaries of the second memoryarray, and boundaries of the third memory array. In one embodiment, theperipheral circuit devices may include sense amplifiers and decodercircuits for the one or more respective first memory array, the secondmemory array, and the third memory array. In one embodiment, theperipheral circuit devices may further include data bus switchingdevices that are configured to control data transfer between the firstmemory array, the second memory array, and the third memory array. Inone embodiment, the peripheral circuit devices may further include thinfilm transistor devices located at least one of the first interconnectlevel and the second interconnect level. In one embodiment, the memorystructure 300 may include computing logic devices located at thesemiconductor material layer of a die, wherein the data bus couples thecomputing logic devices to the first memory array, the second memoryarray, the third memory array, and the peripheral circuit devices.

The various embodiments disclosed herein may provide advantages forcertain computing applications that require fast and very high-bandwidthmemory access. In applications in neuromorphic computing and machinelearning, for example, multiple fast high-bandwidth memory arrays areneeded. The various embodiments disclosed herein may overcome drawbacksof conventional memory architectures by providing a memory structurehaving multiple memory arrays formed on a single die. In this regard,disclosed embodiments may include an SRAM memory array formed at asemiconductor material level of a die, a 1T1C array formed above theSRAM array on the same die, and a 3-dimensional FRAM array formed abovethe 1T1C array on the same die.

The memory structure may further include a data bus that allows massivedata IO between the three memory arrays (i.e., the first memory array,the second memory array, and the third memory array). For example, inone embodiment the data bus may be a 1024 bit data bus. Peripheralcontrol devices may further be provided at the semiconductor materiallayer and may be configured to control data transfer between the variousmemory arrays. Placing such control circuitry below the 1T1C and FRAMarrays reduces the overall area of the memory structure and allows databus connections to be shorter, thereby improving speed and bandwidth ofmemory access. In some embodiments, bandwidth may be increased byfactors of between 32 and 64 relative to conventional memory structures.Similar increases in the speed of data transfer may be achieved incertain embodiments.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of this disclosure.Those skilled in the art should appreciate that they may readily use thepresent disclosure as a basis for designing or modifying other processesand structures for carrying out the same purposes and/or achieving thesame advantages of the embodiments introduced herein. Those skilled inthe art should also realize that such equivalent constructions do notdepart from the spirit and scope of this disclosure, and that they maymake various changes, substitutions, and alterations herein withoutdeparting from the spirit and scope of the present disclosure.

What is claimed is:
 1. A method of fabricating a memory structure,comprising: forming a first memory array located in a first memoryregion of a die, the first memory array comprising an array of SRAMmemory devices; forming a second memory array located in a second memoryregion of the die, the second memory array comprising an array of 1T1Cmemory devices; forming a third memory array located in a third memoryregion of the die, the third memory region comprising an array of FeFETmemory devices; forming at least one data bus laterally extending acrossthe first memory region, the second memory region, and third memoryregion and configured to provide data transfer among the first memoryarray, the second memory array, and the third memory array; and formingperipheral circuit devices at a semiconductor material layer of the die,the peripheral circuit devices configured to control the first memoryarray, the second memory array, and the third memory array.
 2. Themethod of claim 1, wherein: forming the at least one data bus furthercomprises forming a plurality of interconnect level structures; formingthe first memory array further comprises forming the SRAM memory deviceson the semiconductor material layer of the die; forming the secondmemory array further comprises forming the 1T1C memory devices over afirst interconnect level structure of the plurality of interconnectlevel structures; forming the third memory array further comprisesforming the FeFET memory devices over a second interconnect levelstructure of the plurality of interconnect level structures; and formingthe peripheral circuit devices further comprises configuring theperipheral circuit devices to provide control access across arrayboundaries.
 3. The method of claim 1, wherein the peripheral circuitdevices comprise sense amplifiers and decoder circuits for the one ormore of the respective first memory array, the second memory array, andthe third memory array.
 4. The method of claim 3, wherein forming theperipheral circuit devices further comprises forming data bus switchingdevices that are configured to control data transfer between the firstmemory array, the second memory array, and the third memory array. 5.The method of claim 3, wherein forming the peripheral circuit devicesfurther comprises forming thin film transistor devices located at one orboth of a first interconnect level and a second interconnect level. 6.The method of claim 1, further comprising: forming computing logicdevices located on the semiconductor material layer of the die, whereinforming the at least one data bus further comprises coupling thecomputing logic devices to the first memory array, the second memoryarray, the third memory array, and the peripheral circuit devices. 7.The method of claim 1, further comprising forming one or more of thesecond memory array and the third memory array as a 3-dimensional memoryarray including word lines that are shared between two or more stackedactive device layers within the 3-dimensional memory array.
 8. A methodof controlling a memory structure, comprising: receiving and storingdata to a first memory array located in a first memory region of a die,the first memory region comprising an array of SRAM memory devices;transferring data from the first memory array to a second memory arraylocated in a second memory region of the die, the second memory regioncomprising an array of 1T1C memory devices; and transferring data fromthe first memory array and/or from the second memory array to a thirdmemory array located in a third memory region of the die, the thirdmemory region comprising an array of FeFET memory devices, wherein thedata is transferred among the first memory array, the second memoryarray, and the third memory array via at least one data bus laterallyextending across the first memory region, the second memory region, andthird memory region, and wherein the transfer of data among the firstmemory array, the second memory array, and the third memory array iscontrolled by peripheral circuit devices formed at a semiconductormaterial layer of the memory structure.
 9. The method of claim 8,wherein transferring data among the first memory array, the secondmemory array, and the third memory array further comprises: controllingdata bus switching devices to control common bit lines that areswitchably shared between the first memory array, the second memoryarray, and the third memory array to thereby transmit data among thefirst memory array, the second memory array, and the third memory arrayvia the common bit lines.
 10. The method of claim 8, whereintransferring data among the first memory array, the second memory array,and the third memory array further comprises: controlling word linesthat are formed as lateral interconnect structures that couple memorydevices in a plurality of active device layers.
 11. The method of claim8, wherein transferring data among the first memory array, the secondmemory array, and the third memory array further comprises: controllingperipheral devices formed as thin film transistor devices located in thesecond memory region and the third memory region.
 12. A method offorming a memory structure, comprising: forming a first memory region ata semiconductor material layer of a die; forming a second memory regionover the first memory region; and forming a third memory region over thefirst memory region, wherein the first memory region, the second memoryregion, and the third memory region are all formed on a single die. 13.The method of claim 12, further comprising: forming a first interconnectlevel structure over the first memory region prior to forming the secondmemory region such that the first interconnect level structure separatesthe second memory region from the first memory region; and forming asecond interconnect level structure over the second memory region priorto forming the third memory region such that the second interconnectlevel structure separates the second memory region from the third memoryregion.
 14. The method of claim 12, further comprising: forming at leastone data bus that is laterally extending across the first memory region,the second memory region, and the third memory region; and electricallyconnecting the at least one data bus to the first memory region, thesecond memory region, and the third memory region.
 15. The method ofclaim 14, wherein forming the at least one data bus further comprises:forming the at least one data bus to comprises common bit lines that areswitchably shared between the first memory region, the second memoryregion, and the third memory region such that the at least one data busis configured to switchably transfer data among the first memory region,the second memory region, and the third memory region.
 16. The method ofclaim 12, further comprising: forming peripheral circuit devices at thesemiconductor material layer; and electrically connecting the peripheralcircuit devices to the first memory region, the second memory region,and the third memory region, wherein forming the peripheral circuitdevices at the semiconductor material layer further comprises formingthe peripheral circuit devices to be located beneath the second memoryregion and beneath the third memory region.
 17. The method of claim 16,further comprising: forming additional peripheral devices as thin filmtransistor devices including sense amplifiers and decoder circuitslocated in at least one of the second memory region and the third memoryregion.
 18. The method of claim 12, wherein: forming the first memoryregion further comprises forming a first memory array of volatile memorydevices; forming the second memory region further comprises forming asecond memory array of non-volatile memory devices; and forming thethird memory region further comprises forming a third memory arrayconfigured as a 3-dimensional memory array comprising word lines thatare shared between a plurality of stacked active device layers withinthe 3-dimensional memory array.
 19. The method of claim 18, wherein:forming the first memory region further comprises forming a first memoryarray of SRAM memory devices; forming the second memory region furthercomprises forming a second memory array of 1T1C memory devices; andforming the third memory region further comprises forming a third memoryarray of FeFET memory devices.
 20. The method of claim 18, whereinforming the third memory region further comprises: forming the wordlines as vertical interconnect structures that couple memory devices ofthe 3-dimensional memory array that comprises the plurality of stackedactive device layers.